LARTTE: A Posynomial-Based Lagrangian Relaxation Tuning Tool for Fast and Effective Gate-Sizing and Multiple Vt Assignment

In this paper, we propose a novel method for fast and effective gate-sizing and multiple Vt assignment using Lagrangian Relaxation (LR) and posynomial modeling. Our algorithm optimizes a circuit’s delay and power consumption subject to slew rate constraints, and can readily take process variation into account. We first use SPICE to generate accurate delay and power models in posynomial form for standard cells, then formulate a large-scale, convex optimization problem based on these models. Finally, we perform LR to solve for the globally-optimal set of transistor sizes and Vts (with discretization) for each gate. Our key contribution is that we show for the first time that using posynomial models, LRbased circuit tuning can be carried out in a ”generalized” or nonGauss-Seidel manner for improved accuracy. Experimental results show that our implemented tuning tool, LARTTE, exhibits linear runtime and memory usage requirement, can effectively tune a circuit with over 15,000 variables and 8,000 constraints in under 7 minutes, and can minimize the probability of final delay variation by introducing a margin of separation between the worst output arrival time and all other outputs’ arrival times.